11 Dec 2019

San Jose, California Cobham Gaisler announced today at the RISC-V Summit in San Jose, California, that it will release a new line of processor Intellectual Property (IP) cores that implements the RISC-V instruction set architecture (ISA). The NOEL-V processor IP core, the first product in the family, will be made available on 25 December for download into Xilinx’ Kintex UltraSCALE FPGAs.

Cobham is a Gold-Level Member of the RISC-V Foundation, which directs the future development and adoption of the RISC-V instruction set architecture (ISA), an open, free instruction set architecture that enables a new era of processor innovation through open standard collaboration. Cobham also announced today a new LEON5 processor core, further broadening its portfolio of SPARC processors.

“It has been a smooth process to take our vast experience from previous RISC processor core developments for space application and put all that into the design of the new NOEL-V processor targeting also terrestrial applications. Our goal has been to create a solution that can compete with other RISC-V implementations and at the same time be useful for our traditional space customers. And we are also releasing the base version in the free open source variant of our VHDL IP core library, in tradition with what we have done in the past with our processor IP cores.” said Nils-Johan Wessman, RISC-V Project Manager, Cobham Gaisler.

“Cobham is delighted to add our first in-house implementation of a RISC-V processor core to our existing processor portfolio,” said Sandi Habinc, General Manager, Cobham Gaisler. “The addition of a product line of RISC-V processors strengthens Cobham’s abilities to offer reliable processor solutions to customers also outside the space domain.” For more information about Cobham Gaisler's NOEL-V processor, please visit www.caes.com/noel-v.

“For nearly 20 years, Cobham’s LEON processors, which are based on the open SPARC ISA, have been used in RadHard and High Reliability microelectronics solutions in hundreds of spacecraft due to their rich feature set and dependability,” said Jan Andersson, Director of Engineering, Cobham Gaisler. “We intend to release products based on the RISC-V ISA in parallel with the further development of our LEON SPARC processor based products, including the LEON5 processor core.”

“Xilinx is pleased to see Cobham Gaisler expand its offering with NOEL-V to bring the RISC-V ISA to its processor IP portfolio,” said Simon George, Director Embedded Platforms Marketing. “As an emerging open source processor architecture, NOEL-V is now a viable option for soft core processing in our space focused FPGA portfolio.”

The initial RISC-V product will be an RV64GC compliant processor Intellectual Property (IP) core, a 64-bit architecture, written in VHDL. The processor will be fully integrated with Cobham’s GRLIB VHDL IP core library. GRLIB offers a plenitude of interfaces and functions such as high-speed serial interconnect, encryption, compression, etc., to which the RISC-V processor can interface. It will be complemented with the upgrade of the GRMON3 Software Debug Monitor to support the new ISA.

About Cobham Advanced Electronic Solutions

Cobham Advanced Electronic Solutions (CAES), the U.S. subsidiary of Cobham plc operating under a Special Security Agreement (SSA) with the US Department of Defense, provides a number of mission-critical and specialized solutions for harsh environments.

Cobham Advanced Electronic Solutions supplies defense, aerospace, security, medical and industrial markets with critical solutions for communication on land, at sea, and in the air and space, by moving data through off-the-shelf and customized products and subsystems including RF, microwave, and high reliability microelectronics, antenna apertures and motion control solutions. www.caes.com