Overview
Image
CertusPro
CertusPro™-NX-RT FPGAs are purpose-built for space missions with SnPb solder ball leads and are produced from single, traceable wafer lots that have passed radiation acceptance testing. 
These small, power-efficient FPGAs have 96K logical cells that are supported with 7.3Mb of on-die memory, analog features and wideband interfaces making them ideally suited to efficient, scalable distributed processing architectures.
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Overview
Key Tech Specs

Key Features:

  • 28 nm FD-SOI technology for SWaP and radiation performance
  • 96K programmable logic cells
  • 7.3 Mb (EBR and LRAM) embedded memory
    • Max Image Size (with maximum LRAM and EBR) is 22.333 Mb
  • Gen1/2/3 PCIe, SGMII/XGMII (Gigabit Ethernet), LVDS, LVCMOS and more interfaces
  • Dual 1 MSPS, 12-bit SAR ADCs
  • Expert radiation and FPGA technical support
  • Comprehensive suite of development tools and fault-tolerant libraries
  • Programmable Core
    • Low-power mode
    • High-performance mode
    • High embedded memory count
    • DSP blocks
  • High Bandwidth Interfaces
    • 8 SERDES lanes up to 10 Gbps
    • Flexible multi-protocol PCS
    • Supports 10GE, PCIe Gen3, DP/eDP, sLVS-EC, CoaXPress
  • Fast Programmable I/O
    • Diff I/O (1.5 Gbps)
    • LVDS, subLVDS, SGMII
    • DDR3 (1066 Mbps)
    • Up to 306 total I/O

Physical:

  • Plastic package, SnPb balling (x484)
  • 19 mm x 19 mm, 0.8 mm pitch

Operational Environment:

  • Temperature Range: -40°C to 125°C
  • Total Ionizing Dose: <100 krad (Si)
  • SEL Immune: ≤80 MeV-cm2/mg

Power:

  • 600 mW (typical)

Voltage:

  • Supply Voltage (Core): 1.0V
  • Supply Voltage (Aux): 1.8V
  • I/O Voltage Range: 1.0V - 3.3V

Primary I/O:

  • LVDS
  • Soft D-PHY
  • SGMII
  • PCIe
  • GbE

Phase-Locked Loop (PLL):

  • 4

SERDES:

  • 8 Lanes

Supported Memory:

  • DDR2/3L x8, x16, x32 & x64
  • LPDDR2/3/4  x8, x16, x32 &x64

ADC:

  • 2x 1 MSPS
  • 12-bit SAR

Security:

  • Bit stream encryption (AES-256) & authentication (ECDSA)
Key Tech Specs
Downloads

Product Brief

Advanced Product Brief for Frontgrade Certus FPGAs

 

Datasheet

UT24CP1008

 

ADEPT Notifications

SPO-2023-PA-0003
SERDES functional capability limitation when channel 3 is used and PMA clock divider is set to >=2

Downloads
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