The UT8ER2M32 is a 64Mb, radiation hardened by design, high performance CMOS static RAM multichip module (MCM) that is functionally compatible with traditional 2Mx32 SRAM devices. Autonomous (master) and demanded (slave) scrubbing continues while deselected.
The device has a power-down feature that reduces power consumption by more than 90% when deselected, offered in a single package solution, and has superior SEU performance. Ideal for code execution in high performance microprocessors, microcontrollers and FPGAs.
- Features:
- 64Mb, 2M x 32
- Asynchronous Interface
- Embedded EDAC – Master or Slave versions
- 22ns Read, 10ns Write Access Time
- Functionally compatible with traditional 2M x 32 SRAM devices
- CMOS compatible input and output levels
- Three-state bidirectional data bus
- Supply Voltage: +2.3V to +3.6V (Supply), +1.7V to +2.0V (Core)
- Applications:
- Microprocessors, microcontrollers, FPGAs
- Operational Environment:
- Temperature Range: -55°C to +105°C
- Total Ionizing Dose: <100 krad (Si)
- SEL Immune: ≤110 MeV-cm2/mg
- SEU Rate: <8.1 x E-16 errors/bit-day
- Physical:
- 132-Pin Side-Brazed Dual Cavity Ceramic Quad Flatpack
- Power:
- 2W
- Flight Grade:
- QML-Q, QML-Q+, QML-V
- Export Control Classification Number (ECCN):
- 9A515.e.1
- SMD Number:
- 5962-10203
ADDITIONAL SPECIFICATIONS
Datasheet
Application Notes
App-Note-SRAM-ReadOperations.pdf
Memory Power Calculator
Spreadsheet_MemoryPowerCalculator_final ver2016.1.xlsx
IBIS Model
ADEPT Notifications
SPO-2022-PA-0002
During a test program review, it was discovered that input leakage was not measured on input pin /Scrub for all slave stacked SRAMs. This issue covers only slave devices and not master devices. No devices have failed at the customer and is considered a low risk.
SPO-2020-PA-0006D
Group D Seam Seal failure of microcircuit, memory, digital, CMOS, radiation-hardened, dual-voltage SRAM, Multichip Module
SPO-2015-PIN-0003
Product Information Notice is to inform the industry about the CAES SRAMs low power read architecture
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