UT54LVDS032LVT Quad CMOS Differential Line Receiver with Integrated 100 Ohm Termination Resistors

Part Number SMD Part Number Flight Grade LET (MeV-cm^2/mg) TID krad(Si) Supply Voltage Throughput Package
UT54LVDS032LVT 5962-04201 QML-Q, QML-V ≤100 1000 +3.3V 400 Mbps 16-Lead FP

Datasheet

Application Note

ADEPT Notifications

IBIS Models

The UT54LVDS032LVT is a quad CMOS differential line receiver with integrated 100 Ohm termination resistors designed for applications requiring for ultra-low power dissipation and high data rates.

The device supports data rates of 400.0Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. All pins support cold spare buffers and the integrated resistors reduces component cost and saves board space.

Features:

  • Quad Receiver
  • >400.0 Mbps (200 MHz) switching rate
  • ±340mV nominal differential signaling
  • 3.3 V power supply
  • TTL compatible inputs
  • Cold sparing all pins
  • Nominal 100Ω Integrated Termination Resistor
  • 3.3ns maximum, propagation delay
  • 350ps maximum, differential skew
  • Compatible with IEEE 1596.3SCI LVDS
  • Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard

Applications:

  • LVDS Communication Systems
  • Microprocessor and FPGA LVDS driver protection

Operational Environment

  • Temperature Range: -55°C to +125°C
  • Total Ionizing Dose: 1 Mrad (Si)
  • SEL Immune: ≤100 MeV-cm2/mg

Physical:

  • 16-Lead Flatpack
  • 50-mil Pitch

Power:

  • 1.25W (Maximum)

Flight Grade:

  • QML-Q, QML-V

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