The UT54LVDS032LVT is a quad CMOS differential line receiver with integrated 100 Ohm termination resistors designed for applications requiring for ultra-low power dissipation and high data rates.
The device supports data rates of 400.0Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. All pins support cold spare buffers and the integrated resistors reduces component cost and saves board space.
- Features:
- Quad Receiver
- >400.0 Mbps (200 MHz) switching rate
- ±340mV nominal differential signaling
- 3.3 V power supply
- TTL compatible inputs
- Cold sparing all pins
- Nominal 100Ω Integrated Termination Resistor
- 3.3ns maximum, propagation delay
- 350ps maximum, differential skew
- Compatible with IEEE 1596.3SCI LVDS
- Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
- Applications:
- LVDS Communication Systems
- Microprocessor and FPGA LVDS driver protection
- Operational Environment
- Temperature Range: -55°C to +125°C
- Total Ionizing Dose: 1 Mrad (Si)
- SEL Immune: ≤100 MeV-cm2/mg
- Physical:
- 16-Lead Flatpack
- 50-mil Pitch
- Power:
- 1.25W (Maximum)
- Flight Grade:
- QML-Q, QML-V
- Export Control Classification Number (ECCN):
- 9A515.e.2
- SMD Number:
- 5962-04201
ADDITIONAL SPECIFICATIONS
Datasheet
Application Notes
App-Note-UT54LVDS_UT200SpW_FaultPropagation.pdf
App-Note-LVDS-33V-5V-Compatibility.pdf
App-Note-LVDS-ColdSpareFunctionality.pdf
App-Note-LVDS-HBM-ESD-Ratings.pdf
App-Note-LVDS-LVDM-Compatibility.pdf
App-Note-LVDS-FailsafeBiasing.pdf
App-Note-LVDS-ReceiverInputThresholds.pdf
App-Note-LVDS-PowerDissipation.pdf
App-Note-LVDS-PropagationDelays.pdf
App-Note-LVDS-TheoryOfOperation.pdf
ADEPT Notifications
SPO-2022-PCN-002
All CAES LVDS products – HBM ESD ratings added to Data Sheet (DS) and SMD documents
IBIS Model
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