Are you curious about starting a new engaging role, at a world-leading company that works towards European Space Agency and NASA? Then this is your opportunity. We are continuously looking for experienced hardware and software engineers. We welcome your application!
Access our career page or contact us through career (at) gaisler.com.
Ever wonder which microprocessor to use in your space system design?
Check out this white paper which discusses the differences between LEON/SPARC and NOEL-V/RISC-V architectures. The paper describes our past and ongoing component development and explains the rationale for some architectural design choices for future roadmap products. Included herein are trends in the Space industry that are driving key new features example application use-cases and tradeoffs from a software perspective of a legacy LEON/SPARC design vs. a new RISC-V architecture.
Access the white paper
The NOEL-V is a synthesizable VHDL model of a processor that implements the open RISC-V architecture from the RISC-V International organization.
This is the first released model in the RISC-V product line of processors. Seven different configurations are now available for NOEL-V, ranging from a tiny 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors. Click here for more information.
Dual-Core LEON3-FTGR712RC Radiation-hard Dual-Core LEON3-FT Processor, 200 MIPS, 200 MFLOPS |
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Quad-Core LEON4-FTGR740 Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS, QML-V/QML-Q |
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GR740 CG625 |
The GR740 component has received QML-V and QML-Q quality certification by DLA in Q2 2022. Access the GR740 SMD 5962-21204.
Quad-Core LEON4-FTGR740-PBGA Plastic Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS |
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NOEL-V processor model GRLIB IP Library 2024.1-b4292 GR712RC user's manual 2.16 GR712RC data sheet 2.5 GR740 user's manual 2.6 GR716A data sheet 3.2 GR718B user's manual 3.8 GR716B data sheet 0.7 |
GRMON3 Debug Monitor 3.3.10 GRMON2 Debug Monitor 2.0.99 TSIM3 LEON Simulator 3.1.10 TSIM2 LEON/ERC32 Simulator 2.0.66 BCC Bare-C Compiler 2.2.4 RCC RTEMS Compiler 1.2.25, 1.3.2 VxWorks 7 support for LEON VxWorks 6.9 support for LEON |
LEON/GRLIB examples for Lattice Certus/Pro-NX-RT |
We are headed to the Space Symposium in Colorado Springs. Meet us at booth 1313 (North Hall) to discover our technologies and discuss how we can elevate your applications.
This year Frontgrade Gaisler will embark on a grand tour across North America, visiting, presenting and exhibiting at major space events, to connect with our valued customers. Don't miss the opportunity to meet us in person at these events. Swing by our booth to discover the latest innovations and solutions we have in store for you. We are extending an invitation to schedule a meeting through your local sales representative. Whether it's at the conference or at your own premises nearby, we're eager to have meaningful discussions tailored to your specific needs.
Meet us at CHARM - Chalmers Studentkårs Arbetsmarknadsdagar, the Chalmers University of Technology's career fair. Join us at our booth to explore exciting career opportunities!
Access the event.
We have together with Klepsydra Technologies (AI), a leading provider of artificial intelligence (AI) software solutions, announced an initiative to adapt AI algorithms to run on microprocessors used in space missions. This effort is part of a contract recently awarded to Klepsydra by the European Space Agency - ESA to port Klepsydra AI to Frontgrade Gaisler’s GR740 and NOEL-V processors, enabling high performance and reliable AI applications.
Read the press release.
We are exhibiting at the #HiPEAC24 conference, the premier European forum for experts in computer architecture, programming models, compilers, and operating systems. We will also hold a presentation about designing a RISC-V SoC with the NOEL-V Processor and the GRLIB IP Library.
Access the event.
We are exhibiting at the IP SoC Conference, an event organized by Design & Reuse fully dedicated to Silicon Intellectual Property (IP) and IP-based electronic systems. Come and meet us and don't miss our presentation "GRLIB: VHDL IP library for fault-tolerant SoC", from our colleague Fabio Malatesta.
Access the event.
Sandi Habinc, our General Manager, delivered a presentation at the Brave Days 2023, conference organized by NanoXplore at the ESA Space Research and Technology Centre (ESTEC). He officially announced that our GR765 quad-core processor will incorporate a 30k LUT embedded FPGA from NanoXplore. The GR765 will be implemented on the same 28nm FDSOI process from STMicroelectronics as the NG-ULTRA and ULTRA300 FPGA devices.
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Christian Sayer, our Field Application Engineer, will give a presentation at MEWS (Microelectronics Workshop), organized by JAXA (Japan Aerospace Exploration Agency). Christian will explore the GR765, a high-performance space-grade system-on-chip we are developing, which will implement both the SPARC and the RISC-V architectures. The GR765 is a perfect match for the keywords of the conference: "Next-Generation digital devices".
Access the event.
We are exhibiting at EDHPC 2023, the first European Space Power Conference. Meet us at booth 25 and don't miss our presentations about the GR765 octa-core SoC, the GR716 microcontroller, and the GRLIB VHDL IP library.
Access the event.
In the world of advanced technology and exploration, some missions take us where ordinary microprocessors cannot dare to go. Read our last blog: we will uncover some techniques behind the creation of the space microprocessors. The blog is published by RISC-V International.
Read the blog here.
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